Today I’ve search for papers whose subject is the relationship between design space exploration and event-driven simulation. I’ve found out two papers which may be interesting to read. I’ve glanced through both of them for the chief ideas they expose.
These are the papers and the ideas I’ve got after skimming them:
- Efficient design space exploration in PICO. Santosh G. Abraham et al. Hewlett-Packard Laboratories, Palo Alto, CA. Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems, San Jose, California, United States, 2000, Pages: 71 – 79.
- Efficient event-driven simulation of parallel processor architectures. Alexey Kupriyanov at al. University of Erlangen-Nuremberg, Germany. Proceedings of the 10th international workshop on Software & compilers for embedded systems, Nice 2007, Pages: 71 – 80.
The main ideas I could grasp from (Abraham, 2000)
They advocate the concept of hierarchical design space exploration which consists of decomposing the system into components that interact minimally with each other, then evaluating each component in isolation to determine the best design for the individual components, afterwards putting together combinations of these designs to build complete system designs and finally evaluating these systems to determine the best system designs, this way reducing the number of complete designs that are evaluated to a small fraction of the size of the entire design space.
Here are some excerpts:
…The basis for this work is that large-scale systems are often characterized by hierarchical structure and their designs usually have to meet multiple objectives that are incommensurable. (p. 78 at 6. Related work)
…Our approach addresses the important class of design problems where the design space is discrete, optimization metrics are not continuous and may not have a functional representation, and hence concepts such as derivatives are not defined. (p. 78-79 at 6. Related work)
NOTE: Is this related to synfora PICO platform? :)
The main ideas I could grasp from (Kupriyanov, 2007)
ASIPs one-core to parallel processor architectures at ISS level are said to be akin to MPSoCs. The authors use an ISS built from a XML-based description within an event-simulation framework (C++) optimized by formal methods (i.e DDG: Data Dependence Graph), “simulated event patterns” and determining the activity periods . Finally they compare the performance of this approach with commercial tools like modelSim and LisaTek.
Here are some excerpts:
…To allow for high speed simulation of large processor arrays, the challenge is to simulate only in those regions of processor array currently performing a computation. (p. 73 at 4. Event-driven Simulation)
…We defined the simulation model of each processor element by a data dependence graph and further presented an event-driven simulation methodology optimized by (1), introduction of simulation-event-patterns and by (2), determination of activity-periods. We also developed a modeling environment called WPPA Framework which automatically generates a C++ simulation model either from the graphical input or directly from the XML-based architecture description on instruction set level. (pp. 79-80 at 8. Conclusions)