fast event-driven simulation for design space exploration


Today I’ve narrowed my yesterday previous search and I’ve focused on looking for ideas and methods for fast event-driven simulation for design space exploration. I’ve find out a couple of papers about the Artemis SESAME project which is a 2001/2002 project which aimed at efficient simulation of SoC architecture designs and produced a pioneering framework for doing it.

These are the papers:

There also a PhD. thesis that also has relevant content related to the use of this framework.

Ideas from (Terpstra, 2001)

The paper tries to deal with heterogeneous MPSoCs efficient DSE. It outlines the design issues on which to evaluate the performance impact:

  1. new architecture designs,
  2. application to architecture mappings, i.e., which application tasks are mapped onto which architecture components,
  3. different hardware/software partitioning, i.e. which application tasks are implemented by software and which ones are implemented by hardware; stepwise refinement approach through simulation at multiple levels of abstraction

They comment on two tools: spade, which covers (2) and (3) and sesame, which covers (1) The Artemis methodology consists on separating application and architecture models.

The paper doesn’t offer in deep understanding of why the framework is so efficient save the development of a library of template models for common architecture components which enables the reuse of such architecture model components. Is there a relationship between the reuse of components and the reuse of simulation results from those components? It seems to me that a valid relationship implies the use of the component context in their previous usage! So maybe that is the key, I mean, making explicit the reusable component context.

By reusing components maybe past simulation results of those components could also be reused, provided that there also exists a mechanism to detect the presence of these reused components and a way to integrate these past results without incurring in a big error estimation.

I’ve also found the open source place of the sesame project and two related projects sinaxe and xmlpl.

I think the scope which covers the paper is beyond platform based DSE where we have a parametrizable but somewhat fixed hardware platform which determine the HW/SW partition and a flexible application to architecture mapping (i.e which is explored by the MULTICUBE run-time DSE)

There is another related European project tool (CAMELLIA) called CASSE but i haven’t found the source download so I hink it’s not open source!

Ideas from (Pimentel, 2002)

This paper goes on the same idea: instead of co-simulating the SW and HW parts in one simulation, Artemis pushes the separation of modelling application behaviour and modelling architectural constraints at the system level to its extremes and such separation leads to efficient exploration of different design alternatives while also yielding a high degree of reusability.

Responder

Introduce tus datos o haz clic en un icono para iniciar sesión:

Logo de WordPress.com

Estás comentando usando tu cuenta de WordPress.com. Cerrar sesión / Cambiar )

Imagen de Twitter

Estás comentando usando tu cuenta de Twitter. Cerrar sesión / Cambiar )

Foto de Facebook

Estás comentando usando tu cuenta de Facebook. Cerrar sesión / Cambiar )

Google+ photo

Estás comentando usando tu cuenta de Google+. Cerrar sesión / Cambiar )

Conectando a %s