The key to keep up pace with the advance in research and development in electronic system level design and electronic industry in general is having the right information sources, stright from the horse’s mouth as they say. One of those information sources is SCDSource news portal. In that portal good professionals in the field write very interesting articles.

Here are some examples related with the project multicube I’m taking part:

In My Opinion

Defining best practices will aid multicore development

A large number of technologies are available for multicore software development, leaving programmers confused and unsure how to proceed, says Intel’s Max Domeika. A new Multicore Association working group may help by identifying “best practices.”

By Max Domeika, Intel 07/29/08

At the June 2008 Design Automation Conference, I was on a panel entitled “Multi-Processor SoCs — The Next Generation,” and my main position was that it is primarily system developers who need help in the multicore era. The industry can build processors with a large number of cores. The primary issue is making it as easy as possible for developers to extract the benefit.


Contributed Article

How high-level modeling speeds low-power design

By modeling at a higher level of abstraction, you can greatly increase IC power savings, according to Mentor Graphics’ Glenn Perry. He shows an example in which a transaction-level simulation found a power spike that RTL simulation would have missed.

By Glenn Perry, Mentor Graphics Corp. 07/29/08

Low power design used to fall within the categories of cell phones, laptops and hearing aids. Alternatively, if a device was wired to a power outlet, there was little concern for power consumption. However, times have changed — and power optimization is front and center for nearly every design team.

While low power concerns have historically been driven by customer demand for convenience (such as talk time or standby time) the economic and environmental impact of power have become truly compelling realities in the broader electronics market. For example, the fact that every watt of power dissipated costs between 1-2 watts of cooling power commands the attention of corporations paying the electric bills who have hundreds, thousands, and even tens of thousands of computers, routers and related IT equipment in use.

News Analysis

Inside Intel’s ‘smart SoC’ architecture and design flow

Promising a new category of Internet-savvy system-on-chip designs, Intel has outlined its vision for off-the-shelf “smart SoCs.” We look at the architecture and design flow behind the first offering, the Intel EP80579 “integrated processor.”

By Richard Goering 07/28/08

Promising a new category of Internet-savvy system-on-chip designs, Intel has outlined its vision for off-the-shelf “smart SoCs.” The company’s first offering is the EP80579, a configurable chip design aimed at security, storage, communications, and industrial robotics.

Intel claims that smart SoCs represent a new category of “purpose-built” SoC designs. The company promises new levels of performance, power efficiency, and complexity compared to previous SoCs. What distinguishes this effort from some of Intel’s previous forays into the microcontroller market is that the new SoCs will be based on the Intel x86 instruction set architecture. Intel currently has over 15 smart SoC projects underway, most based on the Intel Atom processor.



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