Comienza el DAC 2008


Esta semana se celebra en Anaheim, California, la edición número 45 del DAC (design automation conference) Este es el evento más importante en el campo del diseño electrónico que se celebra al otro lado del atlántico (aquí en Europa tenemos el DATE, Design, Automation, and Test in Europe) Habrá que estar atento a las comunicaciones y presentaciones que tengan lugar por si son relevantes para el proyecto multicube.

De momento, para abrir boca, he encontrado un página web (“My Cheesy Must See List for DAC 2008” por John Cooley Contract ASIC
designer and E-mail Synopsys Users Group (ESNUG) runner) donde se comentan las cosas más relevantes que no se debe uno perder en la feria. En concreto para el tema que nos interesa comenta lo siguiente:

6.) If you’re into ANSI design, CebaTech is showing their C2R Compiler,
which takes untimed ANSI C and outputs Verilog RTL. “Supports
control and data path equally well plus floating point libraries.”
(booth 760) Ask for Chad Spackman. Freebie: mints on keychains

If you’re into SystemC design, Forte Cynthesizer v3.4 adds support
for Power Compiler for “best-in-class area, performance, and now
power results” and “management of ECOs by graphically mapping RTL
back to the original SystemC design” and inter-block interfaces.
(booth 1645) Ask for Brett Cline. Freebie: caricatures

If you’re into C++ design, Mentor is barking about their Catapult C
synth & Vista ESL tools. What’s new this year? They said nothing.
(booth 2301) Ask for Shawn McCloud. Freebie: iPod earbuds

If you’re into Verilog-RTL-to-C conversion for simulation (instead
of C-to-Verilog-RTL for design), check out Carbon’s Model Studio.
It’s more for architects and SW guys wanting models before silicon.
(booth 2467) Ask for Bill Neifert. Freebie: stuffed soccer balls

Synfora Pico Extreme also plays in C, but I’m not sure exactly how.
(booth 329) Ask for Vinod Kathail. Freebie: none

If you want to piss off all the C people, check out Bluespec with
its proprietary “general purpose high-level synthesis & simulation
for modeling, verification and implementation
“. Transactional.
(booth 2367) Ask for Steve Allen. Freebie: electronic Sudoku

Simon Davidmann’s new company, Imperas, sort of lands here with
what appears to be yet-another-ISS tool, OVPsim, for embedded SW.
(booth 467) Ask for Duncan Graham. Freebie: leather beer coaster

Mirabilis VisualSim does “graphical SystemC TLM 2.0 import without
any code development; and power estimation of the full system.”
( booth 778 ) Ask for Deepak Shankar. Freebie: none

En esas pocas líneas he podido recorrer más o menos el estado del arte de las herramientas de desarrollo de sistemas electrónicos con el acento en el design flow desde la especificación (o el algoritmo en C) hasta la implementación con la realización de los procesos de verificación y análisis en la etapa de diseño. Además tengo una abanico de actores dentro del mundo de la industria del diseño con ideas frescas sobre el design flow de sistemas electrónicos. Todo esto va a venir bien para multicube.

Otro sitio que conviene mirar es la columna del pasado 12 de mayo en SOCcentral escrita por Grant Martin de Tensilica en donde se repasan las tendencias que van a mostrarse en el congreso:

ESL Trends: What to Look for at DAC 2008

May 12, 2008 — DAC 2008, in Anaheim, California, is almost here (June 8 to 13). This year, the DAC committee has expanded the number of pre-conference workshops and ancillary events, which makes a crowded ESL calendar even more crowded. Every year, DAC provides a chance to re-calibrate your opinion about ESL as reflected by the wider EDA community both North American and worldwide. So, I’d like to suggest some ESL trends worth looking for in DAC 2008 workshops, panels, technical suggestions and ancillary events.

[…]

By Grant Martin, Chief Scientist, Tensilica, Inc.

Before joining Tensilica as Chief Scientist, Grant worked for Cadence Design Systems for 9 years, eventually becoming a Cadence Fellow in its Labs; Nortel/BNR in Canada for 10 years; and Burroughs in Scotland for 6 years. He received his Bachelors and Masters degrees in Mathematics (Combinatorics and Optimization) from the University of Waterloo, Canada, in 1977 and 1978.

Grant is a co-author or co-editor of nine books dealing with SOC design, SystemC, UML, modeling, EDA for integrated circuits and system-level design, including the first book on SOC design published in Russian. His most recent book, “ESL Design and Verification”, written with Brian Bailey and Andrew Piziali, was published by Elsevier Morgan Kaufmann in February, 2007.

He was co-chair of the DAC Technical Program Committee for Methods for 2005 and 2006. His particular areas of interest include system-level design, IP-based design of system-on-chip, platform-based design, and embedded software. Grant is a Senior Member of the IEEE.

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